1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory, and more particularly, to a bi-directional Fowler-Nordheim (FN) write/erase flash memory utilizing a compatible and low-electric consumption operation mode. An induced capacitor is created between a cell N well and an underlying deep P well to help stabilize source line voltage during read operations. According to the present invention, high-speed code flash memory and high-density data flash memory can be integrated on a single chip.
2. Description of the Prior Art
Recently, flash electrically erasable programmable read-only memories (EEPROMs) have gained substantial interest as the best solution for electrically rewritable nonvolatile data storage. These semiconductor memories, which have been broadly used on digital products such as digital cameras, cell phones, video game apparatuses, personal digital assistants (PDA), and so on, combine the high integration density and the high programming speed of EPROMs with the higher functionality of EEPROMs by offering electrical in-circuit erasability. In general, flash memories are categorized into NOR cell and NAND cell types. As known in the art, NOR type flash memory can be operated at higher read speeds and is thus suited for code flash, which primarily implements program transformation. NAND type flash memory has a relatively low read speed but higher density so that it is typically used as data flash, which primarily implements data access or data storage.
Please refer to FIG. 1. FIG. 1 is a cross-sectional view illustrating a conventional NAND type EEPROM 10. As shown in FIG. 1, the NAND type EEPROM 10 comprises an N-type semiconductor substrate 12, a P-type semiconductor well 14 located in the semiconductor substrate 12, a plurality of NAND cell blocks (B1, B2˜BN) in one column located on the P-type semiconductor well 14, and a local bit line BL1 located over the column of NAND cell blocks (B1, B2˜BN). The prior art NAND type EEPROM 10 further comprises another column of NAND cell blocks (not shown) next to the column of NAND cell blocks (B1, B2BN) of FIG. 1, and both columns of NAND cell blocks are formed on the same (commonly used) P-type semiconductor well 14 having a well depth that is deeper than the depth of STI regions. Each of the NAND cell blocks (B1, B2BN) comprises a plurality of rewritable NMOS memory transistors (M0˜MN) connected in series along a direction of the local bit line BL1. The rewritable NMOS memory transistors (M0˜Mn) are a stacked gate structure, as known in the art, each having an upper control gate 20 and a lower floating gate 22 for storing charges. Rows of word lines are connected to the control gates 20 of memory transistors (M0˜Mn). At two opposite ends of each of the NAND cell blocks (B1, B2˜BN) are provided a bit line selection transistor SGB and a source line selection transistor SGS, respectively, where one terminal of the bit line selection transistor SGB is electrically connected to the local bit line BL1, and one terminal of the source line selection transistor SGS is electrically connected to a source line SL.
However, the above-mentioned flash memory architecture has a drawback in that it consumes a great deal of electricity during a data program operation, leading to a decreased duration of batteries used in digital products. When implementing a data program operation regarding the prior art NAND type EEPROM 10, by way of example, a high voltage such as 20V is applied on a selected word line, and a high voltage such as 12V is applied to unselected word lines to conduct N channels thereof. Consequently, the prior art NAND type EEPROM 10 has very high power consumption. Furthermore, since high voltages, for example, 20V (for the selected cell) and 12V (for non-selected cells), are required to be applied on the selected and un-selected word lines, the programming speed is decelerated, and corresponding reliability problems such as junction breakdown or over-erase will occur. Moreover, since the operation mode of the prior art NAND flash is different from the operation mode of conventional NOR flash, it is difficult to integrate both types of memories onto a single chip. This is because NAND-type data flash memory utilizes a Fowler-Nordheim (FN) tunneling mechanism to implement data programming, while the NOR-type code flash utilizes a hot-carrier injection mechanism to implement data programming. In addition, the prior art flash memory occupies more chip area, thus more costly.